The present invention generally relates to chip packaging structures for high speed chip to chip communication and methods of making the structures; and more specifically to chip packaging structures and methods that do not require an interposer containing through vias and/or exhibit reduced warping.
In the electronic packaging field, there is a drive to develop thinner and larger structures. In 3D chip stacks, chips or dice are layered on top of one another in a three-dimensional stack with electrical interconnects between layers. This configuration has many benefits, such as providing a designer with the ability to place an increased number of chips in a given two-dimensional area with an increased amount of electrical communications between them. In 2.5D packages, an interconnect substrate known as an interposer is used to provide high density interconnects. The interposer is placed between the substrate and the dice, where the interposer contains through silicon vias (TSVs) connecting the metallization layers on its upper and lower surfaces.
One of the main challenges encountered in the development of interposer technology is the process of front-to-back contacts in the interposer. The state of art for front-to-back contacts is to fabricate vertical electrical connections (vias) in the interposer. A typical process is first to drill through holes in the interposer base material, say silicon, then backfill the holes with metal, e.g. copper. The hole drilling process adds significant cost to the product, which is even more challenging for non-silicon material such as glass. Thus, the cost of a large interposer is significant. Through holes drilling and through vias fabrication remain technical challenges for interposers other than silicon, as well as for thick silicon interposers.
In addition, there are further challenges with the 3D and 2.5D chip packages, including adequately controlling heat dissipation and minimizing warping due to the mismatch in mechanical properties of the various layers of the structures made from materials having different coefficients of thermal expansion (CTE). Thin, large interposers often have issues with warpage and assembly.
Flip-chip technology includes methods for interconnecting semiconductor devices, such as integrated circuit (IC) chips to external circuitry using solder bumps that have been deposited onto chip pads. The solder bumps are deposited on the chip pads on a top side of a wafer to mount the chip to external circuitry (e.g., a circuit board or another chip or wafer). The wafer is flipped over so that its top side faces down, and aligned so that its pads align with matching pads on the external circuit, and then the solder is flowed to complete the interconnect. This technique is in contrast to wire bonding, in which the chip is mounted upright, and wires are used to interconnect the chip pads to external circuitry.
There remains a need in the art for the development of new chip package designs that are more cost effective and which provide structural stability to the overall package and adequate communication capabilities between chips and between chips and the chip carrier.